i have component store previous data. current code follows:
process(data_in) variable prev_data : std_logic_vector (7 downto 0) := "00000000"; begin if (prev_data /= "11110000") case(data_in) when "00011100" => en <= '1'; count <= 62500; when "00110010" => en <= '1'; count <= 50000; when others => en <= '0'; count <= 0; end case; else en <= '0'; count <= 0; end if; prev_data := data_in; end process; i update prev_data after comparison has occurred. have tried setting signal no avail. appreciated.
thanks
in future, specify in question problem synthesis related, among technology target , tool using.
as david pointed out, code describe latch triggered change on bit of data_in. not synthesizable tool far know. besides, latches should not used.
any memory element (beside latch) need clock signal operate, following code work fine:
architecture rtl of some_entity signal prev_data : std_logic_vector(7 downto 0); begin process(clk) begin if rising_edge(clk) prev_data <= data_in; if (prev_data /= "11110000") case(data_in) when "00011100" => en <= '1'; count <= 62500; when "00110010" => en <= '1'; count <= 50000; when others => en <= '0'; count <= 0; end case; else en <= '0'; count <= 0; end if; end if; end process; end architecture rtl; you need add clock signal entity.
